Quantum Circuit Template Matching Optimization Method for Constrained Connectivity

The execution of quantum algorithms requires two key considerations. On the one hand, it should meet connectivity constraint requirements circuit mapping for architectures, and on other needs to consider reducing probability errors in circuits as much possible. This paper proposes a novel optimization technique based template matching that satisfy both requirements. method can significantly reduce number gates further enhance its practicality. It stands advanced technology available today. Our optimizes logic mapped onto architecture by initially selecting their linear substructure. We then zone according gate dependency graph optimize each block through matching. Finally, we reorganize obtain optimized version final result. proposed is amenable various architectures. To evaluate efficacy, conduct comparative analysis with t|ket⟩ Qiskit compiler using set benchmark test circuits. Specifically, compare method, highest average rate our reach 25.75%. Compare 32.72%. Overall, approach has significant advantages.